Write signal generator with delay calibration

ABSTRACT

An aligned write signal generator with alignment calibration utilizes an alignment unit to align a plurality of write signal. The aligned write signal generator includes a write signal generator for receiving an EFM signal and converting the EFM signal into a plurality of write signals according to a write strategy waveform generating rule, an alignment unit for receiving the plurality of write signals, aligning the write signals and outputting phase adjusted write signals, and a phase calibration unit for receiving the phase adjusted write signals, detecting phase error between the phase adjusted write signals, and outputting phase control signals. The alignment unit further receives the phase control signals to adjust the delay time of each write signal.

This application claims the benefit of the filing date of TaiwanApplication Ser. No. 092116882, filed Jun. 20, 2003, the content ofwhich is incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to a write signal generator in an optical diskdrive, and more particularly to an aligned write signal generator withdelay calibration in an optical disk drive utilizing an alignment unitto align the write signals with each other in time.

2. Description of the Related Art

FIG. 1 illustrates a block diagram of a laser power control system in aconventional optical disk drive. Referring to FIG. 1, the laser powercontrol system 10 includes an EFM (Eight-to-Fourteen Modulation) encoder11, a write signal generator 12, a LD driver (Laser diode driver) 13,and a LD (Laser Diode) 14. The EFM encoder 11 receives the input dataand generates the EFM signal according to the EFM encoding rule. Thewrite signal generator 12 receives the EFM signal and converts the EFMsignal into a plurality of write signals, e.g. three write signals WS1,WS2, WS3 as shown in FIG. 1, according to the write strategy waveformgenerating rule. The write signal generator 12 typically includes awrite strategy pulse generator 121, a flip-flop unit 122, and a writesignal calculator 123. The LD driver 13 receives the plurality of writesignals and integrates them into a drive signal to drive the LD 14. Howthe write signal generator 12 converts the EFM signal into a pluralityof write signals according to the write strategy waveform generatingrule is a well-known art in this filed and can be found in U.S. Pat. No.6,445,661, so detailed descriptions thereof will be omitted.

Along with increase in write speed of the optical disk drive, the timingaccuracy among the write signals becomes more critical. Correspondingly,the problems of the waveform deformation caused by the digital logicgate, buffer, and output driver within the write signal generator alsobecome more serious owing to, for example, the different delay timeamong the write signals. FIG. 2 shows the ideal waveforms of three writesignals and the corresponding drive signal, wherein FIG. 2A shows threewrite signals generated by an ideal write signal generator, and FIG. 2Bshows the drive signal generated by the LD driver. Because the threewrite signals WS1, WS2 and WS3 are not deformed, the drive signalgenerated by the LD driver is consequently quite ideal.

FIG. 3 shows the deformed write signals and the corresponding drivesignal, wherein FIG. 3A shows three write signals generated by the writesignal generator 12, and FIG. 3B shows the drive signal generated by theLD driver. As shown in FIG. 3, because the three write signals WS1, WS2and WS3 are not aligned in phase (or say, not aligned in time), thedrive signal generated by the LD driver is seriously deformed. If theoptical disk drive outputs such a deformed drive signal to the LD 14,the data may not be recorded in the optical disk in a proper format,thereby causing data error when one tries to reproduce the data in theoptical disk. Therefore, it is an important subject to provide phaseadjusted write signals.

SUMMARY OF THE INVENTION

In view of the above-mentioned problems, an object of the invention isto provide an aligned write signal generator capable of aligning thewrite signals in time, wherein the device calibrates the phase delaysbetween the write signals in advance, and then adjusts the delay time ofeach write signal to align the phase of the write signals.

To achieve the above-mentioned object, the aligned write signalgenerator of the invention includes a write signal generator forreceiving the EFM signal and converting the EFM signal into a pluralityof write signals according to a write strategy waveform generating rule,an alignment unit for receiving the plurality of write signals, aligningthe phase of the write signals, and outputting a plurality of phaseadjusted write signals, and a phase calibration unit for receiving thephase adjusted write signals outputted from the alignment unit,detecting phase differences between the phase adjusted write signal, andoutputting phase control signals. The alignment unit further receivesthe phase control signals to adjust the delay time of each write signal.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a block diagram of a laser power control system in aconventional optical disk drive.

FIG. 2A shows ideal write signals.

FIG. 2B shows a drive signal generated by the LD driver according to thewrite signals in FIG. 2A.

FIG. 3A shows deformed write signals.

FIG. 3B shows a drive signal generated by the LD driver according to thewrite signals in FIG. 3A.

FIG. 4 illustrates a block diagram of a laser power control systemcontaining an aligned write signal generator according to the presentinvention.

FIG. 5 illustrates a block diagram of an alignment unit and a phasecalibration unit of FIG. 4 according to a first embodiment of theinvention.

FIG. 6 illustrates a block diagram of the delay unit and the delay timecontrol unit of FIG. 5.

FIG. 7 illustrates a block diagram of the alignment unit and the phasecalibration unit of FIG. 4 according to a second embodiment of theinvention.

FIG. 8 illustrates a block diagram of the delay unit and the delay timecontrol unit of FIG. 7.

FIG. 9 shows a flow chart of a calibration method for the aligned writesignal generator according to the present invention.

DETAILED DESCRIPTION OF THE INVENTION

The aligned write signal generator with alignment calibration in anoptical disk drive of the present invention will be described withreference to the accompanying drawings.

The conventional laser power control system utilizes the write signalgenerator to generate a plurality of write signals and then directlyoutputs them to the LD driver without the process of detecting whetherthe write signals are aligned in phase (or equivalently, in time) ornot. Usually, a conventional write signal generator will introducedifferent phase delay to different write signal due to the differentsignal processing path. In order to solve this problem, the inventionutilizes a phase calibration unit to detect the phase differences (orequivalently, the delay differences) between the write signals, and analignment unit to adjust the phase (or equivalently, the time delay) ofthe write signals, such that the write signals outputted to the LDdriver are substantially aligned in phase.

FIG. 4 illustrates a block diagram of a laser power control system 40with an aligned write signal generator 48 of the present invention. Thelaser power control system 40 includes an EFM encoder 41, an alignedwrite signal generator 48, a LD driver 43 and a LD 44. The aligned writesignal generator 48 includes a write signal generator 42, an alignmentunit 45 and a phase calibration unit 46. The EFM encoder 41 receives theinput data and generates the EFM signal according to the EFM encodingrule. The write signal generator 42 receives the EFM signal and convertsthe EFM signal into a plurality of write signals, e.g. three writesignals WS1, WS2 and WS3 as shown in this embodiment, according to thewrite strategy waveform generating rule. The alignment unit 45 receivesthe write signals WS1, WS2 and WS3, respectively delays the writesignals WS1, WS2 and WS3, and generating phase adjusted write signalsAWS1, AWS2 and AWS3 for output. A LD driver 43 receives the phaseadjusted write signals AWS1, AWS2 and AWS3 and generates a drive signalto drive a LD 44. The architectures and functions of the write signalgenerator 42, the LD driver 43, and the LD 44 are the same as those ofthe prior art, and detailed descriptions thereof will be omitted. Thephase calibration unit 46 receives and detects the phase errors of thephase adjusted write signals AWS1, AWS2 and AWS3 during calibrationmode, and outputs phase control signals to the alignment unit 45.

The aligned write signal generator 48 of the invention has two operationmodes, including a calibration mode and a normal mode. In thecalibration mode, the phase error between the write signals arecalibrated before the laser power control system 40 starts to write. Thenormal mode is the general write mode of the aligned write signalgenerator 48. When the aligned write signal generator 48 is in thenormal mode, the phase calibration unit 46 is disabled and the alignmentunit 45 is utilized to delay each write signal according to the delaysetting obtained in the calibration mode so as to align the phase ofthese write signals.

When the aligned write signal generator 48 is in the calibration mode,the phase calibration unit 46 is enabled and receives the phase adjustedwrite signals AWS1, AWS2 and AWS3, detects the phase errors among thephase adjusted write signals, and then generates the phase controlsignals. The alignment unit 45 adjusts the delay time of each writesignal according to the phase control signals.

FIG. 5 illustrates a block diagram of an alignment unit and a phasecalibration unit of FIG. 4 according to a first embodiment of thepresent invention. Referring to FIG. 5, the alignment unit 45 includesthree delay units 451, 452 and 453 for respectively receiving the writesignals WS1, WS2 and WS3. Each delay unit delays the write signal andoutputs the phase adjusted write signal. The number of delay unitscontained in the alignment unit 45 is determined according to the numberof write signals outputted from the write signal generator 42.

Referring again to FIG. 5, the phase calibration unit 46 includes aswitch 463, a PD (phase detector) 464, a charge pump 465, an integrator466, and a delay time control unit 467. The phase calibration unit 46detects the phase error between two selected write signals, andoutputting the phase control signals to the alignment unit 45. The phasedetector 464 receives the phase adjusted write signal AWS1 and one ofthe phase adjusted write signals AWS2 and AWS3 outputted from the switch463. Because the phase detector 464 detects the phase error between twoinput signals and outputs a detection signal, the phase calibration unit46 utilizes the switch 463 to switch the phase adjusted write signalsAWS2 and AWS3 according to a switch signal.

The PD 464 detects the phase error between a first input signal A and asecond input signal B and outputs control signals UP and DN to controlthe charge pump 465 according to the phase error, wherein the firstinput signal A is the phase adjusted write signal AWS1, and the secondinput signal B is the signal outputted from the switch 463. If the phaseof the first input signal A leads that of the second input signal B, thepulse width of the control signal UP is larger than the pulse width ofthe control signal DN. Thereby the charge pump 465 generates a positivecontrol current Icp. On the contrary, if the phase of the first inputsignal A lags behind that of the second input signal B, the pulse widthof the control signal UP is smaller than the pulse width of the controlsignal DN. Thereby the charge pump 465 generates a negative controlcurrent Icp. The calibration circuit utilizes the integrator 466 tointegrate the control current Icp and then to output an error voltageVerr. The delay time control unit 467 generates the phase controlsignals for adjusting the delay time of each delay unit of the alignmentunit 45 according to the error voltage Verr.

FIG. 6 illustrates a block diagram of the delay unit and the delay timecontrol unit 467 of FIG. 5. As shown in FIG. 6, the delay unit 451 (452,453) is composed of a plurality of serially connected delay cells 61, amultiplexer 62, and a counter 63. The delay cells 61 receive the writesignal, generate a plurality of delayed signals with different delaytime, and output the delayed signals to the multiplexer 62. Themultiplexer 62 selects one of the delayed signals for output accordingto the selecting signal (delay time) outputted by the counter 63. Thecounter 63 outputs the count value as the selecting signal.Consequently, the delay time of the delay unit may be changed accordingto the count value of the counter 63.

The delay time control unit 467 includes comparators 65 and 66, ANDgates 67 and 68, and a switch 69. The comparator 65 compares the errorvoltage Verr with a first reference voltage V1 and generates a firstcomparison signal. The comparator 66 compares the error voltage Verrwith a second reference voltage V2 and generates a second comparisonsignal. The AND gate 67 receives a trigger clock SC and the firstcomparison signal to generate an up-counting signal. The AND gate 68receives the trigger clock SC and the second comparison signal togenerate a down-counting signal. The switch 69 receives the up-countingsignal and the down-counting signal for outputting the up-countingsignal and down-counting signal as the phase control signals to thecounter 63 in one of the delay units according to the switch signal. Thecounter 63 counts the pulse number of the up-counting signal and thedown-counting signal as the delay time. Consequently, according to thearchitecture of FIG. 6, when the error voltage Verr is higher than thefirst reference voltage V1, it means that the first input signal A leadsthe second input signal B. So, the AND gate 67 will generate a pulse inthe up-counting signal at each rising edge of the trigger clock,therefore the counter will up-count in order to increase the delay timeof signal B. Alternatively, when the error voltage Verr is lower thanthe second reference voltage V2, it means that the first input signal Alags behind the second input signal B. So, the AND gate 68 will generatea pulse in the down-counting signal at each rising edge of the triggerclock, therefore the counter will down-count in order to decrease thedelay time of signal B. Of course, the delay unit shown in FIG. 6 isjust one of the embodiments, other embodiments of the delay unit capableof achieving the function are also fully supported by the presentinvention.

In addition, when the phase calibration unit calibrates the phase errorof the write signals WS1 and WS2, the phase control signals containingthe up-counting signal and the down-counting signal are outputted to thecounter in the delay unit 452 through the switch 69 according to theswitch signal. When the phase calibration unit calibrates the phaseerror of the write signals WS1 and WS3, the phase control signalscontaining the up-counting signal and the down-counting signal areoutputted to the counter in the delay unit 453 through the switch 69according to the switch signal. The switch 69 may be a pure switch or ade-multiplexer. In the embodiment of FIG. 5, the delay time of each ofthe write signals WS2 and WS3 are adjusted on the basis of the writesignal WS1. Because the phase of the write signals WS2 and WS3 may leador lag behind the write signal WS1, it is preferable to set the countvalues of the counters in the delay units 451 of the alignment unit 45to one half of the maximum count value. By choosing one of the writesignals as reference, it needs only to adjust the delay time (countvalues) of the delay units associated with the other write signals toachieve alignment among all the write signals. Furthermore, the counterin the delay unit may be a counter with a reload function and thecounter is reloaded an initial value at the beginning of calibration.

FIG. 7 illustrates a block diagram of the alignment unit 45 and thephase calibration unit 46 of FIG. 4 according to a second embodiment ofthe present invention. In the first embodiment, the aligned write signalgenerator 48 utilizes the phase calibration unit 46 to calibrate thephase error between the write signals WS1, WS2 and WS3, which areinputted to the first alignment unit 45, without considering the delayerror caused by the phase calibration unit 46 itself. In view of this,in addition to a switch 463, a PD 464, a charge pump 465, an integrator466, and a delay time control unit 467′, the phase calibration unit 46′of the second embodiment further includes a multiplexer module 461 and asecond alignment unit 462, and utilizes the multiplexer module 461 andthe second alignment unit 462 for calibrating the delay error caused bythe phase calibration unit 46′ itself. After the delay calibration ofthe phase calibration unit 46′ is finished, the phase error of the writesignals WS1, WS2 and WS3 are calibrated as in the first embodiment.

The multiplexer module 461 includes three multiplexers for selecting thephase adjusted write signals AWS1, AWS2, AWS3 or the calibration clockCLK to output. The second alignment unit 462, which is the same as thefirst alignment unit 45, also includes three delay units 4621, 4622 and4623 for respectively delaying the output signals of the multiplexermodule 461. When the circuit calibrates the delay error of the phasecalibration unit 46′, the control signal CAL1 is enabled to make themultiplexer module 461 output the calibration clock CLK to the secondalignment unit 462. Thereafter, the phase calibration unit 46′ utilizesthe loop, including the second alignment unit 462, the PD 464, thecharge pump 465, the integrator 466, and the delay time control unit467′, to calibrate the delay error due to the phase calibration unit46′, especially caused by the switch 463. The delay time of each delayunit of the second alignment unit 462 is adjusted in a way similar thatdescribed in FIG. 6. In the example given in FIG. 7, once the delayunits of the second alignment unit 462 are well adjusted, the path delayof the following paths: the path from signal AWS1 input of the phasecalibration unit 46′ to the signal A input of the PD 464, the path fromsignal AWS2 input of the phase calibration unit 46′ to the signal Binput of the PD 464, and the path from signal AWS3 input of the phasecalibration unit 46′ to the signal B input of the PD 464, will besubstantially the same.

FIG. 8 illustrates a block diagram of the delay unit and the delay timecontrol unit of FIG. 7. The delay time control unit 467′ of FIG. 8 isthe same as the delay time control unit 467 of FIG. 6 except that theswitch 69′ of the delay time control unit 467′ further receives thecontrol signal CAL1. That is, when phase calibration unit 46′ calibratesthe phase calibration unit 46′ itself, the control signal CAL1 isenabled and the switch 69′ will output the phase control signalsincluding the up-counting signal and the down-counting signal to thedelay unit of the second alignment unit 462. On the contrary, when thephase calibration unit 46′ adjusts the delay time of the first alignmentunit 45, the control signal CAL1 is disabled and the switch 69′ willoutput the phase control signals including the up-counting signal andthe down-counting signal to the delay unit of the first alignment unit45.

In addition, because the aligned write signal generator 48 of thisembodiment generates three write signals, the phase calibration units inFIGS. 5 and 7 use the switches 463 to switch different signals forcalibration. However, if the write signal generator only generates twowrite signals, the switches 463 of the phase calibration unit of FIGS. 5and 7 is no longer needed and can be omitted.

FIG. 9 shows a flow chart of a calibration method for the aligned writesignal generator with alignment calibration in an optical disk driveaccording to the present invention. Referring to FIG. 9, the calibrationmethod for the aligned write signal generator of the invention includestwo stages. First stage is to calibrate the delay error of the phasecalibration unit itself, and second stage is to calibrate the phaseerror of the write signal caused by the write signal generator. Thus, inthe phase calibration unit 46 shown in the block diagram of FIG. 5, onlythe second stage is needed because the calibration architecture of thephase calibration unit 46 is not included. The steps of the calibrationmethod of the aligned write signal generator with alignment calibrationof the invention will be described with reference to FIG. 9.

Step S900: start the calibration procedure.

Step S902: enable the control signal CAL1 and set an initial value tothe counter of each delay unit. Because the control signal CAL1 isenabled, the delay time of the phase calibration unit itself iscalibrated.

Step S904: set the switch signal to be a first set of signal. If thenumber of write signal outputted from the write signal generator exceedstwo (three write signals in this embodiment), it is necessary to use theswitch to switch the signal to be calibrated. If there are only twowrite signals outputted from the write signal generator, this step maybe omitted.

Step S906: calibrate the delay time of the delay unit of the secondalignment unit in the phase calibration unit itself according to thecalibration loop.

Step S908: detect whether all of the delay units have been calibrated.If yes, the process jumps to step S912; otherwise the process jumps tostep S910.

Step S910: set the switch signal to be a next set of signal to switchnext signal to be calibrated and jump back to step S906.

Step S912: disable the control signal CAL1 and enable the calibrationsignal. Because the control signal is disabled, the calibration of thedelay time of the write signal generator is performed. To enable thecalibration signal is to ask the EFM encoder to generate the calibrationreference clock, such as all of the write signals have substantial thesame phase.

Step S914: set the switch signal to be a first set of signal. If thenumber of write signal outputted from the write signal generator exceedstwo (three write signals in this embodiment), it is necessary to use theswitch to switch the signal to be calibrated. If there are only twowrite signals outputted from the write signal generator, this step maybe omitted.

Step S916: calibrate the delay time of the delay unit according to thecalibration loop.

Step S918: detect whether all of the delay units have been calibrated.If yes, the process jumps to step S922; otherwise the process jumps tostep S920.

Step S920: set the switch signal to be a next set of signal to switchnext to be calibrated and jumps back to step S916.

Step S922: disable the calibration signal.

Step S924: end the calibration procedure.

While certain exemplary embodiments have been described and shown in theaccompanying drawings, it is to be understood that such embodiments aremerely illustrative of and not restrictive on the broad invention, andthat this invention not be limited to the specific construction andarrangement shown and described, since various other modifications mayoccur to those ordinarily skilled in the art. For example, the phasecalibration unit of the embodiment also may be combined with a PLL.

1. An aligned write signal generator with alignment calibration,comprising: a write signal generator for receiving an EFM signal andconverting the EFM signal into a plurality of write signals according toa write strategy waveform generating rule; a first alignment unit forreceiving the write signals, delaying at least one of the write signalsaccording to a plurality of phase control signals and outputting aplurality of phase adjusted write signals, wherein the first alignmentunit generates a plurality of preset phase adjusted write signals at acalibration mode; and a phase calibration unit for receiving the presetphase adjusted write signals, and detecting the phase errors among thepreset phase adjusted write signals at the calibration mode to adjustthe phase control signals, wherein the phase calibration unit outputsthe adjusted phase control signals at a normal mode.
 2. The alignedwrite signal generator according to claim 1, wherein the EFM signal is acalibration EFM signal when a calibration signal is enabled, so as tomake the write signal generator output the write signals with alignedphase.
 3. The aligned write signal generator according to claim 1,wherein the first alignment unit further receives the phase controlsignals and adjusts delay time of each write signal when the calibrationsignal is enabled.
 4. The aligned write signal generator according toclaim 1, wherein the first alignment unit has a plurality of delayunits, each of delay units comprises: a counter for outputting a countvalue as a selecting signal: a cascaded delay cell module for receivingone of the write signals and outputting a plurality of delayed signalswith different delay time; and a multiplexer for receiving the delayedsignals and selecting one of the delayed signals for output as the phaseadjusted write signal according to the selecting signal; wherein thecounter up-counts or down-counts according to the phase control signals.5. The aligned write signal generator according to claim 1, wherein thephase calibration unit comprises: a phase detector for receiving thephase adjusted write signals and outputting a phase error signal; acharge pump for receiving the phase error signal and generating acontrol current according to the phase error signal; an integrator forreceiving the control current, integrating the control current, and thengenerating an error voltage; and a delay time control unit foroutputting the phase control signals according to the error voltage. 6.The aligned write signal generator according to claim 5, wherein thephase calibration unit further comprises: a selection switch forreceiving the phase adjusted write signals and selecting two of thephase adjusted write signal to be outputted to the phase detector. 7.The aligned write signal generator according to claim 5, wherein thedelay time control unit comprises: a first comparator for comparing theerror voltage with a first reference voltage and outputting a firstcomparison signal, wherein the first comparison signal is of high levelwhen the error voltage is higher than the first reference voltage; asecond comparator for comparing the error voltage with a secondreference voltage and outputting a second comparison signal, wherein thesecond comparison signal is of high level when the error voltage is lessthan the second reference voltage; a first AND gate for receiving thefirst comparison signal and a trigger clock, and generating anup-counting signal; a second AND gate for receiving the secondcomparison signal and the trigger clock, and generating a down-countingsignal; and a switch for receiving the up-counting signal and thedown-counting signal, and outputting the up-counting signal and thedown-counting signal as the phase control signals to one of the delayunits according to a switch signal; wherein the first reference voltageis higher than or equal to the second reference voltage.
 8. The alignedwrite signal generator according to claim 7, wherein the phasecalibration unit further comprises: a multiplexer module having aplurality of multiplexers, each of which has a first input terminal anda second input terminal, wherein the first input terminals of themultiplexers receive a calibration clock, the second input terminals ofthe multiplexers receive the phase adjusted write signal, respectively,and the multiplexer module outputs the calibration clock when a controlsignal is enabled and outputs the phase adjusted write signal when thecontrol signal is disabled; and a second alignment unit comprising aplurality of delay units for respectively receiving the signalsoutputted from the multiplexer module and outputting signals to thephase detector.
 9. The aligned write signal generator according to claim8, wherein the switch outputs the up-counting signal and thedown-counting signal to the delay units of the second alignment unit ofthe phase calibration unit when the control signal is enabled andoutputs the up-counting signal and the down-counting signal to the delayunits of the first alignment unit when the control signal is disabled.10. The aligned write signal generator according to claim 6, wherein thedelay time control unit comprises: a first comparator for comparing theerror voltage with a first reference voltage and outputting a firstcomparison signal, wherein the first comparison signal is of high levelwhen the error voltage is higher than the first reference voltage; asecond comparator for comparing the error voltage with a secondreference voltage and outputting a second comparison signal, wherein thesecond comparison signal is of high level when the error voltage is lessthan the second reference voltage; a first AND gate for receiving thefirst comparison signal and a trigger clock, and generating anup-counting signal, a second AND gate for receiving the secondcomparison signal and the trigger clock, and generating a down-countingsignal; and a switch for receiving the up-counting signal and thedown-counting signal, and outputting the up-counting signal and thedown-counting signal as the phase control signals to one of the delayunits according to a switch signal; wherein the first reference voltageis higher than or equal to the second reference voltage.
 11. The alignedwrite signal generator according to claim 10, wherein the phasecalibration unit further comprises: a multiplexer module having aplurality of multiplexers, each of which has a first input terminal anda second input terminal, wherein the first input terminals of themultiplexers receive a calibration clock, the second input terminals ofthe multiplexers receive the phase adjusted write signal, respectively,and the multiplexer module outputs the calibration clock when a controlsignal is enabled and outputs the phase adjusted write signal when acontrol signal is disabled; and a second alignment unit comprising aplurality of delay units for respectively receiving the signalsoutputted from the multiplexers of the multiplexer module and outputtingsignals to the phase detector.
 12. The aligned write signal generatoraccording to claim 11, wherein the switch outputs the up-counting signaland the down-counting signal to the delay units of the second alignmentunit of the phase calibration unit when the control signal is enabledand outputs the up-counting signal and the down-counting signal to thedelay units of the first alignment unit when the control signal isdisabled.
 13. A method for generating phase adjusted write signals in anoptical disk drive, the method comprising the steps of: generating thepreset write signal to obtain a plurality of preset phase adjusted writesignals at a calibration mode; detecting the phase errors among thepreset phase adjusted write signals at the calibration mode; adjustingat least one of the preset write signals for a delay time according tothe phase errors of the preset phase adjusted write signals at thecalibration mode; obtaining a delay setting at the calibration mode;receiving an EFM signal; converting the EFM signal into a plurality ofwrite signals according to a write strategy waveform generating rule;and delaying the write signals according to delay settings forgenerating the phase adjusted write signals with aligned phase.
 14. Themethod according to claim 13, wherein the step of adjusting the delaysettings comprises the steps of: generating a calibration EFM signal;converting the calibration EFM signal into the plurality of writesignals; and adjusting the delay settings according to the phasedifference among the phase adjusted write signals to make the phase ofthe phase adjusted write signals be substantially aligned.